Accompanying the miniaturization and performance enhancement of electronic equipment in recent years, it has been demanded that semiconductor elements (semiconductor packages) have a higher density and become smaller and thinner. To address this demand, CSPs (Chip Size Packages), which are semiconductor elements whose sizes are reduced to nearly a chip size, are now becoming widespread.
Furthermore, in mobile information equipment etc., a multi-chip module in which semiconductor chips are arrayed and mounted in the plane direction has been employed with the aim of assigning an added value such as a memory or increasing the capacity. In order to reduce the mounting area of this multi-chip module, the configuration called a “stacked package”, in which a plurality of semiconductor chips are stacked to increase the packaging density, has been proposed, and also the stacked package adapted to be a CSP has been proposed (Patent Documents 1 to 10).
FIG. 13 shows a stacked package 1000 disclosed in Patent Document 1. In the stacked package 1000, stacked semiconductor chips 101 and 102 are connected to a wiring layer 104 on an insulating substrate 103 via bonding wires 108, and molded with a resin 109. External terminals 110 used for mounting are formed on the rear surface of the insulating substrate 103. Patent Document 2 also discloses a stacked package with a similar configuration.
Also, there has been proposed a stacked package 1100 in which wire bonding and flip chip bonding are used in combination, as shown in FIG. 14 (see Patent Document 3). In the stacked package 1100 shown in FIG. 14, a semiconductor chip 101 is connected with wires 108 whereas a semiconductor chip 102 is connected with bumps 107, and an underfill resin 105 is formed between the semiconductor chip 102 and the wiring board 103. Patent Documents 4 and 5 also disclose similar configurations.
Furthermore, there has been proposed a stacked package 1200 obtained by stacking a plurality of flash memories 101, each of which is flip-chip mounted on an interposer 111, with spacer substrates 112, 122 intervening therebetween, as shown in FIG. 15 (Patent Document 6). Patent Document 7 also discloses a similar configuration.
Moreover, Patent Documents 8, 9, and 10 disclose stacked packages that basically employ flip-chip mounting. FIG. 16 shows a stacked package 1300 disclosed in Patent Document 8. In the stacked package 1300 shown in FIG. 16, semiconductor chips 101a to 101c are flip-chip mounted using wiring boards 103a to 103c, respectively. A similar configuration is disclosed in Patent Document 9. FIG. 17 shows a stacked package 1400 disclosed in Patent Document 10. In the stacked package 1400 shown in FIG. 17, a semiconductor chip 101 is connected to wiring patterns 104 via bumps 107, whereas a semiconductor chip 102 is connected to wiring patterns 104 via bumps 107 and lead electrodes 113.
Since the stacked packages shown in FIGS. 13 to 17 have configurations in which a plurality of semiconductor chips are stacked, they can achieve a higher packaging density as compared with the case where semiconductor chips are mounted two-dimensionally. However, the inventors of the present invention revealed that the currently proposed configurations of stacked package have the following problems by conducting a keen study without being restricted to existent knowledge. For the sake of simplicity in illustration, FIGS. 18 to 20 show the configurations of the stacked packages 1000, 1100, and 1200 shown in FIGS.13 to 15, respectively, in the forms allowing easy comparison.
First, in the stacked package 1000 shown in FIG. 18, the respective semiconductor chips (101, 102) can be mounted on the wiring board 103 by wire bonding (WB). However, with this configuration, a height (a loop height of the wires 108) sufficient for performing the WB is necessary, and also a large mounting area for performing the WB needs to be provided on the wiring board 103 side. Therefore, it is inevitable that restrictions are imposed on thickness reduction and miniaturization. Furthermore, since this configuration is based on the WB, an area array-type semiconductor chip cannot be used in this configuration while this configuration is applicable to the case where only peripheral-type semiconductor chips are used. Moreover, since the WB is performed for many wires, the manufacturing process becomes complicated as the number of WB steps performed for the respective wires increases. Besides, when performing the WB with respect to the multistage chips, technical difficulties or restrictions are liable to occur. In particular, since the wires used for the uppermost semiconductor chip need to cover a long connection distance, a technique difficulty arises that the loop height of the wires needs to be small.
Next, in the case of the stacked package 1100 shown in FIG. 19, since both the WB and flip chip bonding (FC) are employed, the complication of the manufacturing process by performing both the steps is inevitable. Furthermore, since the WB is employed, the configuration also suffers the restrictions caused by the height (the loop height) of the wires and the mounting area on the wiring board 103 side in the WB, as in the case of the example shown in FIG. 18. Thus, a problem is caused when attempting further thickness reduction and miniaturization.
In the case of the stacked package 1200 shown in FIG. 20, the interposers 111 and the spacer substrates 112 are necessary, which leads to cost increase and also complicates the manufacturing process. Moreover, since the spacer substrates 112 are used, the thickness reduction becomes difficult. In the case of the stacked packages 1300 and 1400 shown in FIGS. 16 and 17, the manufacturing processes are liable to be complicated.                Patent Document 1: JP 11-204720 A        Patent Document 2: JP 2000-349228 A        Patent Document 3: JP 2004-273706 A        Patent Document 4: JP 11(1999)-3969 A        Patent Document 5: JP 2000-294722 A        Patent Document 6: JP 2002-9227 A        Patent Document 7: JP 5(1993)-75015 A        Patent Document 8: JP 2004-153210 A        Patent Document 9: JP 2002-33443 A        Patent Document 10: JP 2002-170921 A        